The present invention relates to a method of improving flatness of a base wafer and suppressing generation of particles in a process for producing the bonded wafer having SOI layer or a silicon active layer.
Recently, public attention has been especially drawn to so called SOI (silicon on insulator) structure having a silicon active layer on a silicon oxide film with electrical insulation property, since it has characteristics of high speed of device, low electricity consumption, high breakdown voltage, high resistance to environment. As a typical method for producing such a SOI wafer having SOI structure, there has been the bonding method.
The bonding method is a technique wherein two silicon wafers are bonded via a silicon oxide film. For example, as shown in Japanese patent publication No. 5-46086, an oxide film is formed on at least one of the wafers, and closely contacted each other without interposing impurities at a contacted surface, and subjected to heat treatment at a temperature of 200 to 1200xc2x0 C. in order to increasing bonding strength. The bonded wafer whose bonding strength is increased by the heat treatment can be then subjected to a grinding and polishing process. Accordingly, the wafer on which a device is fabricated (bond wafer) can be subjected to grinding and polishing process reduce its thickness as desired, and thereby a SOI layer on which a device is formed can be formed.
The bonded SOI wafer produced as above is excellent in crystallinity of the SOI layer, and has an advantage of high reliability of buried oxide layer just under the SOI layer. However, the thickness thereof is reduced by grinding and polishing, which process takes long time for reducing thickness. Moreover, material is wasteful Furthermore, film thickness uniformity is generally in the range of xc2x10.5 xcexcm of target thickness, which has been the largest technical subject of technology. As a method of reducing a film thickness for solving a problem of film thickness uniformity in the bonding method, there have been developed a so-called PACE (Plasma Assisted Chemical Etching) method disclosed in Japanese Patent publication No. 2565617, and a hydrogen ion delamination method (occasionally called smart-cut method) disclosed in Japanese Patent Application Laid-open (Kokai) No.5-211128.
PACE method is a method for making film thickness of SOI layer uniform according to vapor phase etching wherein SOI wafer produced by the bonding method (thickness of the SOI layer is several xcexcmxc2x10.5 xcexcm) is prepared, distribution of thickness of the SOI layer to be uniform is measured to make a map of thickness distribution, thick part is removed by vapor phase etching (plasma etching) with control of value according to the map, so that the SOI layer with very thin and uniform thickness can be formed.
The hydrogen ion delamination method is a method wherein an oxide film is formed on at least one of two silicon wafers; at least one of hydrogen ions and rare gas ions is implanted into the upper surface of one of the wafers in order to form a fine bubble layer (enclosed layer) within the silicon wafer; the ion-implanted surface is brought into close contact with the other silicon wafer via the oxide film; heat treatment (delaminating heat treatment) is then performed to delaminate a portion of one of the wafers using the fine bubble layer as a cleavage plane (delaminating plane), in order to form a thin film; and heat treatment (bonding heat treatment) is further performed to firmly bond them, to provide an SOI wafer. Although the surface of the SOI wafer produced as above (a delaminated surface) is a relatively good mirror-like surface, it is subjected to a mirror polishing process, called xe2x80x9ctouch polishingxe2x80x9d, wherein a stock removal is very small, in order to provide SOI wafer having surface roughness equivalent to the general mirror polished wafer.
According to this method, an SOI wafer whose SOI layer has a very high thickness uniformity can be obtained relatively easily. Furthermore, the delaminated wafer can be reused, namely there is also an advantage that the material can be efficiently used.
Moreover, silicon wafers can be directly bonded without the oxide film, and it is possible to use the method not only for bonding silicon wafers each other, but also for bonding the ion-implanted silicon wafer to insulator wafer having different thermal expansion coefficient such as quartz, silicon carbide, alumina or the like.
As a result of development of these techniques for reducing film thickness, it has become possible to produce a bonded SOI wafer having SOI layer of very thin thickness of 0.1xc2x10.01 xcexcm and excellent thickness distribution. As a result, use of a bonded SOI wafer has been significantly broaden, and therefore it is expected to be applied to the most advanced device having very fine pattern or a special structure. Furthermore, a similar bonding method can also be applied to a wafer produced by directly bonding the silicon wafers without an oxide film.
In the bonding method, if surface roughness of two silicon wafers to be bonded each other is a mirror polished surface at general product grade, it is possible to produce the bonded wafer without generating bonding failure such as void or the like at bonding interface. Therefore, as a wafer to be used, mirror polished wafer (hereinafter occasionally referred to as PW) having general product grade has been used.
A method for producing PW comprises, as conventionally known, steps of slicing a silicon ingot, and a step of subjecting the resulting silicon wafer to, at least, chamfering, lapping, acid etching, mirror polishing of one surface and cleaning or the like. Depending on the purpose, the order of these steps can be partly changed, some of these steps can be repeated, or other steps such as a heat treatment step, a grinding step or the like can be added or changed thereto. Among these steps, the acid etching step is conducted in order to remove a surface degraded layer due to working of the surface introduced during mechanical machining such as slicing, chamfering, lapping or the like. It is conducted, for example, by etching with an acid mixture comprising hydrofluoric acid, nitric acid, acetic acid and water with an etching amount of several xcexcm to several tens xcexcm from the surface. Regarding this step, the following problems have been pointed out in the step.
1) Flatness of the lapped wafer having a deviation of thickness as expressed by TTV [Total Thickness Variation] (xcexcm), LTVmax [Local Thickness Variation] (xcexcm) or the like is degraded more when the etching amount is more.
2) Waviness having a cycle in mm order or unevenness called peal is generated on the etched surface.
3) Harmful NOx is generated by etching.
Taking these problems into consideration, alkali etching is sometimes used.
Advantages and disadvantages of the alkali etching are explained below.
Advantages are as follows:
a) Flatness after lapping is maintained even after etching.
b) Generation of harmful gas is suppressed.
Disadvantages are as follows:
a) Pits having a depth of several xcexcm and a size of several xcexcm to several tens xcexcm are present locally on the etched surface. Therefore, if impurities get into the pits, they may cause generation of particles and contamination in the following steps.
b) Since deep pits are present, and surface roughness (Ra) is increased, it is necessary to increase stock removal in the following mirror polishing step (mechanochemical polishing).
c) The shape of unevenness of the surface after alkali etching is sharp compared with acid etching treatment. Therefore, such unevenness itself may cause generation of particles.
Meanwhile, the most serious problem in the bonding method before the above-mentioned PACE method and the hydrogen ion delamination method have been developed was uniformity of the thickness of the SOI layer. As described above, since the bonding method comprises bonding a bond wafer to be made thin and a base wafer for supporting it directly or via an oxide film, and making the bond wafer thin by grinding and polishing it, it is very difficult to obtain uniform thickness of the film. Accordingly, it was necessary for obtaining uniform thickness of the film as possible, to improve flatness of the base wafer. Namely, when the bond wafer is ground or polished to be thin, it is conducted on the basis of the back surface of the base wafer. Accordingly, flatness of the base wafer directly affect uniformity of the film thickness of the SOI layer after the bond wafer is made thin.
For the above reason, PW wherein one surface of chemical etched wafer (hereinafter occasionally referred to as CW) produced by alkali etching method that is excellent in flatness was subjected to mirror polishing has been used for a base wafer of a bonded wafer.
According to the above-mentioned PACE method and hydrogen ion delamination method, thickness uniformity of a bonded wafer was significantly improved. However, PW for use as a base wafer can still be made only from CW with excellent flatness produced by alkali etching. The reason therefor is as follows.
As for PACE method, it was found that it is necessary to use a bonded SOI wafer having a thickness of about 5xc2x10.5 xcexcm and thickness uniformity produced by grinding and polishing, when a thin SOI wafer having a thickness of 0.1xc2x10.01 xcexcm is produced. Because, if thickness uniformity is worse than the above-mentioned value, it is not possible to obtain a sufficient effect of compensating deviation of thickness by one time PACE processing, and it is difficult to obtain target thickness and thickness uniformity. As a result, it is necessary to take a margin for work by making SOL layer thickness before PACE processing, and conduct PACE processing plural several times, which may lead to lower productivity and increasing cost.
On the other hand, as for hydrogen ion delamination method, deviation of thickness of SOI layer depends mainly on deviation of hydrogen ion implantation or oxide film thickness before hydrogen ion implantation. Accordingly, SOL layer having uniform distribution of film thickness can be formed regardless of flatness of the base wafer. However, the surface of the formed SOI layer becomes a transcription of the surface of the base wafer. Accordingly, if the base wafer having low flatness is used, deviation of film thickness of the SOI layer is good, but flatness of the surface of the SOI layer of the formed SOI wafer is bad. Accordingly, PW produced from CW with excellent flatness according to alkali etching method has been used as a base wafer also in a hydrogen ion delamination method.
However, with realization of thin film SOI wafer having a film thickness of 0.1xc2x10.01 xcexcm, it becomes necessary to apply to the most advanced device having very fine pattern or a special structure, and generation of particles becomes a main problem among the problems of alkali etching mentioned above. Furthermore, it was made clear that the particles are generated especially at a chamfered part of a base wafer of SOI wafer. The reason therefor is considered as follows. The chamfered part of the wafer is worked to be arched shape and surfaces of various orientation are exposed. Accordingly, if anisotropic etching such as alkali etching is conducted, difference in etching rate depending on the orientation becomes significant, so that uneven shape apt to generate fine particles are made.
As a method for suppressing generation of particles from a chamfered part, Japanese Patent Publication No.2588326 discloses a technique that a chamfered part is polished with a polishing cloth to be a mirror surface. However, this technique is proposed for application to a wafer subjected to acid etching. Accordingly, if it is simply applied to a wafer subjected to alkali etching that is used as a base wafer for SOI wafer, it takes much longer time to finish to be mirror surface, compared to the wafer subjected to acid etching, due to sharp and significant unevenness. Moreover, generation of particles from the back surface of a base wafer cannot be prevented.
The present invention has been accomplished to solve the above-mentioned problems. A main object of the present invention is to provide base wafers for a bonded wafer wherein generation of particles from a chamfered part or a back surface is reduced as possible without lowering flatness of the base wafer and in high productivity, and to provide a bonded wafer wherein very few particles are generated, having SOI layer or silicon active layer excellent in thickness uniformity.
To achieve the above mentioned object, the first method of the present invention provides a method of producing a bonded wafer comprising bonding a bond wafer made of silicon single crystal and a base wafer via an oxide film or directly and then reducing thickness of the bond wafer, wherein the base wafer is a wafer produced by processes comprising slicing a silicon single crystal ingot and then, subjected at least to chamfering, lapping, etching, mirror polishing and cleaning, and the etching process is conducted by subjecting the wafer to alkali etching, and then acid etching, and an etching amount in the alkali etching is larger than an etching amount in the acid etching.
As described above, if the etching process is conducted by subjecting the base wafer after lapping to alkali etching first to remove a damaged layer due to mechanical working with keeping flatness after lapping, and then subjecting it to acid etching, local deep pits remaining after alkali etching is made shallow, and surface roughness and sharp unevenness can be improved to be smooth. Thereby, unevenness itself can be prevented from causing generation of particles in the following mirror polishing process and polishing stock removal can be reduced.
In that case, an etching amount of alkali etching needs to be larger than an etching amount of acid etching. The main reason therefor is as follows. In order to make the local deep pits remaining after alkali etching shallow, an etching amount in alkali etching treatment needs to be larger than the etching amount in acid etching required for decreasing rate of generation of failure such as spot called stain due to unevenness of etching or flatness.
By bonding the bond wafer to the base wafer produced as described above and then reducing its thickness, it will be possible to produce a high quality bonded wafer having high flatness, excellent in thickness uniformity of SOI layer or silicon active layer and generates almost no particles.
In that case, it is preferable that a chamfered part of the base wafer is subjected to a mirror finishing process after the above-mentioned etching process.
As described above, since the chamfered part of the base wafer is apt to generate particles especially during alkali etching in the above-mentioned etching process, further smooth chamfered part from which particles are removed can be produced by conducting mirror finishing after the etching process. Furthermore, if mirror edge polishing is conducted after the above-mentioned two step etching process, polishing time can be significantly shorten compared to the conventional method wherein mirror edge polishing is conducted after alkali etching, and one to several xcexcm of polishing stock removal is sufficient, and therefore productivity can be significantly improved. Accordingly, a base wafer for bonded wafer having high flatness and generating almost no particles can be produced at good yield. Thereby, productivity and cost performance can be improved.
According to the present invention, after bonding a bond wafer to a base wafer, a chamfered part of base wafer can be subjected to a mirror finishing process.
As described above, a chamfered part of base wafer can be subjected to a mirror finishing process after bonding a bond wafer to a base wafer, thereby particles apt to generate at a chamfered part can be removed, so that a bonded wafer having high quality can be produced.
Then, according to the present invention, it is preferable that an etching process is performed by dipping the wafer in an aqueous solution of hydrogen peroxide after conducting alkali etching, and then conducting acid etching.
The surface of the wafer after alkali etching is active, and hydrophobic, so that impurities are easily adhered thereon, namely apt to be contaminated. Thus, if the surface is made hydrophilic by immersing it in the aqueous solution of hydrogen peroxide to oxidize it, particles are hardly adhered thereon.
The above-mentioned etching amount is preferably 10 to 30 xcexcm in the alkali etching and 5 to 20 xcexcm in the acid etching.
Regarding alkali etching, as etching amount increases, a depth of local pits remaining after etching becomes shallow, and surface roughness tends to get worse on the contrary. Accordingly, the above-mentioned range is appropriate. Regarding acid etching, as etching amount increases, flatness gets worse, but a stain generation rate significantly decreases. Accordingly, the above-mentioned range is appropriate.
In the present invention, alkali etching solution can be an aqueous solution of NaOH or an aqueous solution of KOH, and the acid etching solution can be an aqueous solution of mixed acids comprising hydrofluoric acid, nitric acid, acetic acid and water.
Using such an etching solution, etching treatment in an alkali etching or an acid etching can be surely achieved, control of an etching amount is relatively easy, and cost therefor is low. All of the specific value of an etching amount shown in the present invention is total amount of an etching amount of both surfaces of the wafer.
The above-mentioned acid etching is preferably reaction-controlled acid etching.
If the acid etching is reaction-controlled as above, local deep pits remaining after alkali etching, surface roughness and unevenness can be improved, and furthermore, waviness can be improved to make the wafer flatter.
In that case, a solution for reaction-controlled acid etching can be an aqueous solution of mixed acids comprising hydrofluoric acid, nitric acid, acetic acid and water in which silicon is dissolved at concentration of 20 to 30 g/l.
Using such an etching solution, etching treatment can be surely achieved, control of an etching amount is relatively easy, and cost therefor is low.
The second method of the present invention also provides a method for producing a bonded wafer comprising bonding a bond wafer made of silicon single crystal and a base wafer via an oxide film or directly, and then reducing thickness of the bond wafer, wherein the base wafer is a wafer produced by processes comprising slicing a silicon single crystal ingot, and then subjected at least to chamfering, lapping, etching, mirror polishing and cleaning, and the etching process is conducted by subjecting the wafer to acid etching, and the mirror polishing process is conducted on both surfaces.
As described above, the etching process of the base wafer is conducted by acid etching, a degraded layer due to surface processing introduced during mechanical machining such as slicing, chamfering, lapping and the like, and to prevent generation of pits. If both of the surfaces thereof is then subjected to mirror polishing process, flatness can be surely improved, even though flatness is degraded by acid etching. As a result, improvement of flatness and reduction of particles can be realized at the same time. Accordingly, if the bond wafer is bonded to the base wafer, and then thickness is reduced, it will be possible to produce a high quality bonded wafer having high flatness, excellent in thickness uniformity of SOI layer or silicon active layer and having almost no particles.
In that case, it is preferable that a chamfered part of the base wafer is subjected to a mirror finishing process after the above-mentioned etching process.
As described above, if the chamfered part of the base wafer is subjected to mirror finishing after acid etching, time necessary for mirror edge polishing is scarcely increased, and no particles are generated from the chamfered part where particles are apt to be generated. Accordingly, it can be suitable as a base wafer for a bonded wafer.
A chamfered part can also be subjected to a mirror finishing process after bonding a bond wafer to a base wafer also in the second method of the present invention.
As described above, a chamfered part can also be subjected to a mirror finishing process after bonding a bond wafer to a base wafer, thereby generation of particles can be suppressed.
The present invention also provides a bonded wafer produced by the above-mentioned method.
As described above, in the first method or the second method of the present invention, a base wafer constituting a bonded wafer has high flatness is achieved and generation of particles is suppressed, and therefore thickness uniformity of SOI layer or silicon active layer of the bonded wafer obtained by bonding the bond wafer to the base wafer is more excellent, and therefore the wafer can be suitably used for fabrication of a device having extremely fine pattern or special structure.
Furthermore, the present invention also provides a bonded wafer having a base wafer wherein back surface is chemically etched, a chamfered part is mirror surface, and the chemically etched back surface of the base wafer is subjected to acid etching following to alkali etching.
The bonded wafer is, for example, produced by the first method of the present invention. Accordingly, almost no particles are generated from the back surface of the bonded wafer (back surface of the base wafer) and from a chamfered part of the base wafer. Flatness of the back surface of the bonded wafer is extremely high, and thickness uniformity of SOI layer or silicon active layer of the bonded wafer is extremely high.
The present invention also provides a bonded wafer wherein the back surface of its base wafer is chemically etched and a chamfered part is mirror surface, and on the chemically etched back surface, the maximal depth of the pit is 6 xcexcm or less and the average value of waviness is 0.04 xcexcm or less.
As described above, according to the present invention, it is possible to obtain a bonded wafer whose surface is extremely flat, and the depth of pit is shallow.
Furthermore, according to the present invention, a bonded wafer is also provided, wherein waviness having a wavelength of 10 mm is at least 0.5 to 10 xcexcm3 as power spectrum density.
As described above, according to the present invention, a bonded wafer wherein waviness on the back surface of the base wafer is in the above range can be obtained. Namely, the bonded wafer having quite excellent flatness can be obtained.
Additionally, the present invention also provides a bonded wafer wherein at least the back surface and the chamfered part of the base wafer are mirror surface.
As described above, since, in the present invention, the back surface of the base wafer constituting a bonded wafer is mirror surface, flatness is extremely high, and thickness uniformity of SOI layer or silicon active layer is excellent. Furthermore, since the back surface and the chamfered part are mirror surface, no particles are generated from the obtained bonded wafer.
As described above, according to the present invention, there can be produced a base wafer for a bonded wafer wherein flatness of the wafer after lapping can be maintained, waviness of the surface of the wafer after etching can be reduced, and generation of local deep pits and degradation of surface roughness can be suppressed, and contamination such as particles, stains or the like are rarely generated on the mirror chamfered part and the back surface. When the bond wafer is bonded to the base wafer and thickness thereof is reduced, thickness uniformity of SOI layer or silicon active layer of the bonded wafer is extremely excellent. Accordingly, it can be suitably used for fabrication of a device having fine pattern or special structure. Furthermore, almost no prolongation of time for mirror polishing of a chamfered part is necessary in order to make the surface smooth and suppress generation of particles. Accordingly, yield and productivity are improved and cost performance is also improved.